This invention relates to ferroelectric memory, non-volatile memory and embedded memory, and specifically to a two-transistor memory unit exhibiting long term memory retention and low power consumption.
A number of solid state, non-volatile memory devices are known in the art. Flash memory is generally a single transistor memory cell, which may be fabricated in a high packing density array, but which requires high voltage and which has a relatively slow programming process. Electrically Erasable Programmable Read-Only Memory (EEPROM) is a programmable memory array which has similar structural and behavioral characteristics to a flash memory, but which may be selectively erased. A one-transistor one-capacitor ferroelectric random access memory (1T-1C FeRAM) device is similar to a dynamic RAM (DRAM), which has a destructive read-out. The family of 1T FeRAMs is still under development. These devices exhibit high standby leakage current and a low memory retention time, which are the two major obstacles of this family of memories.
Sung-Min Yoon et al., A novel FET-type Ferroelectric Memory with Excellent Data Retention Characteristics, describes a 1T-2C device wherein the data retention durations are enhanced by providing two ferroelectric capacitors, which are polarized in opposite directions, IEDM 2000.
A two transistor ferroelectric non-volatile memory includes a ferroelectric capacitor having an upper electrode and a lower electrode, wherein the upper electrode is connected to a word line; a first MOS transistor includes a linear capacitor located at a gate oxide region thereof, wherein a gate of the first MOS transistor is connected to the lower electrode of the ferroelectric capacitor and wherein a drain of the first MOS transistor is connected to a bit line and wherein the source of the first MOS transistor is connected to a ground; a second transistor having a gate connected to a programming line, a drain connected to the lower electrode of the ferroelectric capacitor, and a source connected to a ground and the source of the first transistor; wherein, when a positive pulse is applied to the word line and to the programming line, the second transistor is switched on and connects the bottom electrode of the ferroelectric capacitor to the ground, a charge is placed on the ferroelectric capacitor thereby creating a xe2x80x9c1xe2x80x9d state in the memory. When a negative pulse is applied to the word line and a positive pulse is applied to the programming line, the second transistor is switched on and connects the bottom electrode of the ferroelectric capacitor to the ground, a charge is placed on the ferroelectric capacitor, thereby creating a xe2x80x9c0xe2x80x9d state in the memory.
It is an object of the invention to provide a FeRAM having non-volatile memory characteristics.
Another object of the invention is to provide a FeRAM having both long memory retention characteristics and low power requirements.
A further object of the invention is to provide a 2T-1C FeRAM.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.